Integrated circuit Static Random Access Memory (SRAM) devices are widely used in electronic systems. Since an SRAM cell generally comprises six transistors, the SRAM cell generally requires more area than a DRAM cell which generally only includes one transistor and one capacitor. Thus, in the SRAM cell, the pitch of the cells should be minimized so as to increase the integration of the devices in an integrated circuit. However, in order to increase the integration of the cells, the cell pattern and the SRAM manufacturing process may become complicated.
An integrated circuit SRAM cell layout was published at the International Electron Devices Meeting (IEDM) in 1985. This SRAM will be briefly described with reference to FIG. 1. According to the SRAM published at the IEDM in 1985, three polysilicon layers (one for forming a gate electrode and the remaining two for interconnection layers) and one metal layer are used to form an SRAM cell with an area of 9.9.times.14.3 .mu.m.sup.2. As shown in FIG. 1, the active region pattern 10 and the pattern 12 of the polysilicon layer used for forming the gate electrode are complicated. Also, the design uses a Vss contact between a node contact and a bit-line contact so as to reduce the cell size. Unfortunately, compared with the conventional Vss contact which is formed parallel to the node contact, the shape of active region 10 is further complicated.
As is known, when patterning the SRAM using lithography, patterns such as the gate electrode and active layer are effected by nonlinearities, distortions and other effects. Thus, as shown in FIG. 2, the edges of the pattern formed on the substrate become rounded. As shown in FIG. 2, due to this rounding, the overlapping portion 24 between the polysilicon layer 22 for forming the gate electrode and the active region 20 is reduced, so that the channel length of the transistor formed in overlapping portion 24 is shortened, compared with FIG. 1. As a result the leakage current of the transistor may increase.
FIG. 4 is a plane view of the conventional SRAM published at the IEDM. As shown in FIG. 4, a polysilicon layer 36 for forming the gate is formed close to the neighboring node contacts A and B. Thus, due to misalignment in the lithography process, a short may occur between the node so contacts A and B and the neighboring polysilicon layer 36. Reference numeral 38 represents a part of the bit-line and reference numeral 39 represents an active region. Also, GND represents a ground line, Vcc represents a power supply line, and IL represents a connection line between the contacts.
In order to solve the above problems, an SRAM was published at the ISSCC (International Solid State Circuits Conference) in 1992. The SRAM published by the ISSCC has a cell area of 8.5.times.12.8 .mu.m.sup.2 and includes one polysilicon layer and two metal layers. One of the metal layers determines the overall layout size of the SRAM. As shown in FIG. 3, the metal layer forms a word-line 32 and a Vcc line 30 in the horizontal direction and a connection line 34 between the contacts in the vertical direction. The cell size is determined by the size of each line and the space between the lines. Since the SRAM cell published by the ISSCC in 1992 uses three layers, which is one less than the SRAM published at the IEDM in 1985, this layout is also relatively simple to fabricate.
Notwithstanding the above improvements, the state of the art continues to desire much smaller SRAM cell layouts for high density integration.